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| MOTOROLA Order this document by MC6840/D s SEMICONDUCTOR TECHNICAL DATA MC6840 Programmable Timer Module (PTM) .!,. A),,),, l.~:~,,.l.,.,$.. :.*L~\,\. The MC6840 is a programmable subsystem component of the M6800 Family designed to provide t,., ,1. ~ ., ~ *:~\ ,:::'~" ,<$,+ variable system time intervals. ){t t,$.~ t.+ \ ":tt+.:?.,:t:'i' The MC6840 has three 16-bit binary counters, three corresponding control registers, and a status \.:?,\\, , + ,,,.F+ ,;&~ \ ~! register. These counters are under software control and may be used to cause system interrupts .'\' :,~>.,,, ~:,~:;,..+ ...+.~...~. . ,.,,. ~<~r.. andlor generate output signals. The MC6840 may be utilized for such tasks as frequency measure~ .<\;: L.4!:s+" \ *Y>:" *. ments, event counting, interval measuring, and similar tasks. The device may be used for square *;L* "- '. ~.\\,\. - ~.t.:~,,, wave generation, gated delay signals, single pulses of controlled duration, and pulse width modul~?~'''*,., ~ .$ tion as well as system interrupts. ,>~+ `$tt MOTOROLA MOTOROLA INC , 1988 = DS9802R3 @ BLOCK DIAGRAM m t E (Enable) & I Rea,ster I A Clock I --. J!{ `,~t.. The average chip-juncti~wt~~$eratu ,$>5, -*, .,d:P:.. 3... ~ .,> re, TJ, in `C can be obtained from: where: TA OJA pD PINT TJ =TA+ (PD*OJA) ;., $ i< ~.s>>,, :<:*, `.~~ ..$.' = Arn~~~m\,fem peratu re, `C = +P@k~d''Thermal Resistance, Junction-to-Ambient, `Cm ,~~~~~+ PpORT , !kd~~ x Vcc, $: (1) Pp~T3W$='*~ort . ,4 ~ ~ *;'.?,,* Watts -- Chip Internal Power Power Dissipation, Watts -- User Determined ~~$@~~#appliCatiOnS ppORT (1) and (2) for K gives: q (TA+2730C) +0JNPD2 K=PD (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA, Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA MOTOROLA 2 MC6840 DS9802R3 MAXIMUM RATINGS Rating Symbol Vcc V,n Value -0.3 to +7.0 -0.3 to +7.0 Oto -40to +70 +85 Unit v v This devtce contains circuitry Inputs voltages vised agatnst that damage fields, due or electric normal to protect to high the static Supply Voltage Input Voltage Operating Temperature Range - TL to TH MC~, MC~A40, MC~B40 MCWOC, M C6BA40C however, it IS adto precautions be taken TA Tstg avoid application of any voltage max!mum rated voltages to `c higher than this htgh- Storage Temperature Range -55to +150 `c tmpedance clrcult. For proper recommended that V,n and strained SVCC. operation It IS Vout be con- THERMAL CHARACTERISTICS Characteristic Symbol 9JA 65 100 Value Unit `cm to the range VSSS(Vln or Vout) Rellabllity of operation IS enhanced~, Inputs level (e unused voltage are tied to an appropr!atewt$~$. g., eltner VSS Thermal Resistance Cerdip Plastic or V@&$ , "'$.~ ~, f?.':),:, DC ELECTRICAL Input High Voltage Input Input Low Voltage Leakage CHARACTERISTICS (VCC = 5.o Vdc + 5%, VSS =0, TA= TL to TH unless otherwise Min Symbol Characteristic VIH vlL Iin DO-D7 DO-D7 Other Outputs m, ITS[ VSS+2.O ,'!>$:` \*,i .,.:?. noted) .,ih ~+., I T~,?.. ~~ Max `;'%`~ Vcc VSS+O.8 2.5 10 -- - VSS+O.4 VSS+0,4 10 7W 12.5 75 5.0 Unit v v PA pA v Current Input (Vin =0 Current to 5.25 V) (Vin= 0.5 to 2,4 V) HI-Z (Off State) Output (lL~ad= (l Load= Output (l Load= Output Internal Input (Vln=O, Output High Voltage -205KA) -2~KA) 1.6 mA) mA) Current Dissipation f=l.O (Off State) (VOH = 2.4 V) at TA= TL) v s s - Q,$ >?'~&:' , .,,. ... . ..5 ~ .,t. "**$*l .0 ..,:<.> $$J .!,. 20 ,.,., ..}}:, t$?,:::% :,::~"}:. 2.4 - - -- -- 1.0 470 -- -- v O H,:.,.? V~~+ Low Voltage f'.$;: ii :,+ ~$:, VSS+2.4 is`i~~.*(5. `*?~,~.s~< -- - -- -- -- (l Load =3.2 Leakage Power DO-D7 .2 `%Q# 01-05?; :&s~' v PA mW pF (Measured MHz) Capacitance TA=250C, .,i.~ `$ILOH ..... -..:*<>. PINT +:$?1$$., tf\ "$ >,,p.,~~.D7 Ci" "?l$~~fl others >. %. .? ,:..>.' IRQ Capacitance TA=25C, f=l.O MHz) (V,n=O. Cn,,t -- -- pF ,. AC OPERATING CHARACTERISTICS (See Figure:Q~!%&;}$* ..i: $+...i$ kAPcaAn I 1 -- MC6BA40 Max 1.0" Min -- MC6BB40 Max 0.666. Characteristic Input Rise and Fall Times (Fiaures 4 and 5) ~. ~, and RESET Min -- Max O.w" Unit I .:cr-~ if "'.?:.: !'+> ~~ I I - Inuut Pulse Width `~As~nchronous C, G, and RESET Low (Figure Input) - 2) :'::$; `3:q>%WL ~,({, ~, : I I 1 -, rvvH , tcyc E + tsu + thd - tcycE+ tsu + thd - tcyc E + tsu + thd - ns Input Pulse Width High (Figw&~~'s'p Input) ~ii~ ~$Y (Asynchronous tcVcE+ tsu + thd , - 1 tcycE+ tsu + thd [ - 1 tcVcE+ tsu + thd - ns -- ns -- thd ion Time (Figure ln~~:pu]se Width Mode On Iv) 50 -- 50 -- w -- ns -- 7) tsvnc pWL, PWH 250 120 -- -- 2m 80 -- -- 175 60 -- -- ns C3'( - 8 Prescaler t TTL MOS CMOS 6) tco tcm tcmos tlR -- -- -- -- 700 450 2.0 1.2 -- -- -- -- 460 450 1.35 0.9 -- -- -- -- Mo MO 1,0 07 ns -- ns ns Us Output Delay, 01-03 (Figure V, Load VDD, B) Load D) Load D) Time 5) (VOH =2.4 (V0H=2.4V, (VOH=O.7 Interrupt tr and tfs Release tcvcE (Figure MC6840 DS9802R3 MOTOROLA 3 BUS TIMING CHARACTERISTICS (COO~1-+=. I z, a,, ~ --~ Q) ,UUG I"" LGa 1, " d, I Ident. Numbr 1 2 3 4 Q Characteristic Cycle Time Pulse Width, Pulse Width, Clock E Low E High MC6840 MC68A40 ..lin tcvc PWEL PWEH tr, tf tAH Max 10 9W 9W 25 - - - - Min 0.67 280 280 - 10 60 60 10 Max 10 9500 9m 25 - - - - I MC68840 Min Max 0.5 210 220 - 10 40 40 10 ~ `nit #s ns ns ns ns ns Q:.ns 1.0 430 4W -- 10 80 80 10 10 9m 9m 20 - - - Rise and Fall Time Hold Time ;s Setup Time Before E E 4.. Address tAS tcs tCH I 14 15 Chip Select Setu Jp Time ,., ,- Before elect Hold Time Chip Sf' `"" 18 21 ! Read Data Write Hold I Ime tDHR1201W01201~. tDHW tDDR tDSW Data Hold Time :ral Output sral Input Data Delay Time Data Setup Time 10 - ~~~ - 290 -- 10 - 80 - 20 I ~ Qs$f" ns ~,Q, $J*,p~;@ I ns I, ] ns I 180 .~ ~.~,'"~j $~ ~!, FI$URE2 ..,\:. `*T: .*} ;?:, * - INPUT PULSE WIDTH LOW FIGURE3 - INPUT PULSE WIDTH HIGH --. MOTOROLA 4 MC6840 DS9802R3 FIGURE4 - INPUT SETUP AND HOLD TIMES FIGURE 5 - OUTPUT DELAY `esrpO'"'T L 300F I -- NOT E: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted. MC6840 DS9802R3 MOTOROLA 5 DEVICE OPERATION The MCW is part of the Mm microprocessor family "open drain" output (no load device on the chip) which permits other similar interrupt request lines to be tied together in a wire-OR configuration. Them line is activated if, and onlv if, the Composite interrupt Flag (Bit 7 of the Internal Status The conditions under which the ~Q discussed RESET in conjunction with Register) is asserted. line is activated are Register. lnt~ !fi@ PTM and is fully bus compatible with MWOO systems. The three timers in the MC~ operate independently and in several distinct modes to fit a wide variety of measurement and synthesis applications. The MCWO is an integrated, set of three distinct counter/timers. It consists of thre'e' 16-bit data latches, three 16-bit counters (clocked independently), and the comparison and enable circuitry necessary to implement various measurement and synthesis functions. In addition, it contains interrupt drivers to alert the processor that a particular function has been completed. In a typical application, a timer will be loaded by first storing two bytes of data into an associated Counter Latch. This data is then transferred into the counter via a Counter initialization cycle. If the counter is enabled, the counter decrements on each subsequent clock period which may be an external clock, or Enable (E) until one of several predetermined conditions causes it to halt or recycle. The timers are thus programmable, inputs or the MPU anv time. BUS INTERFACE cyclic in nature, controllable by external program, and accessible by the MPU at the Status - A low level at this input is clocked by the E (Enable) input. Two Enable pulses a~~.r~~~~d to synchronize and process the signal. Th~ ~$~ then recognizes the active "low" or inactive ~~l~t~~~&ti the third Enable pulse. If the RESET signal is a~yw~~bus, an additional Enable period is required if SQ$U9 ttw$s are not met. The RESET input must be stable ,&@$~P~$$~for the minimum time stated in the AC Operating';:$~,a]ecteristics. Recognition of a low level ~~~hlsh!~put by the PTM causes the following action to o~c~s$~~ COUnt a. All counter latch@' ~r~;$reset to their maximum .JtQ,ff> .,.,.&...,>,,? values. ,'i>:,,...." ~ .,$., :b. c. All Control %${~~bits are cleared with the exception of CRIOJi~~ter~l reset bit) which is set. to the contents of the latches. clocks are The Programmable Timer Module (PTM) interfaces to the M6BO0 Bus with an 8-bit bidirectional data bus, two Chip Select lines, a Read/Write line, a clock (Enable) line, and interrupt Request line, an external Reset line, and three Register select lines. VMA should be utilized in conjunction with an MPU address line into a Chip Select of the PTM when using the MC6800/6802/680B. BIDIRECTIONAL DATA (DGD7) - The bidirectional .data N t~@skU lines (DO-D7) allow the transfer of data between and PTM. The data bus output drivers are t~~$,~$ta$e devices which remain in the high-impedance (Q@),%t$~~ except when (Read/Write tivated). the M PU performs a PTM ~$~~~'~eration and Enable lines high and PT~~$~~~~;Welects ac:*.. i:;?:+ ?,$ ?~ . All cofi'~$~<=.are preset ~:,$..,: .s.,<.,,> ~.~;j,, , d. All@ou~$er outputs are .~;~$w. .':!..:? ~ e. ~$~ Status Register bits ,>..: ` :~"~:,~:. RwlSTER SELECT LINES +'r~it,? reset and all counter (interrupt flags) are cleared. - These in- (RSO, RSl~RS2) :,.,,!.i%:~~ts are used in conjunction with the R/W line to select the , ""* ~t!~i.> , " Internal registers, counters and latches as shown in Table 1. ~ ,,.${ *~:\ \+i .,,. ~t? NOTE The PTM is accessed via MPU Load and Store operations in much the same manner as a memory device. The instructions available with the M6800 family of MPUS which perform read-modify-write operations on memory should not be used when the PTM is accessed. These instructions actually fetch a byte from memory, perform an operation, then restore it to the same address location. Since the PTM uses the R/~ line as an additional register select input, the modified data will not be restored to the same register if these instructions are used. CONTROL REGISTER .,,. , CHIP SELECT (CSO, CS1 ) - T@?e~?W7signals are used to activate the Data Bus interfa~{%k~llow transfer of data from the PTM. With C~O = @~an$ CSI = 1, the device is selected and data transfer,,$~'R~,~% fir. `yi !$ READ/WRITE MPU to control (R/~$+- "$%is signal is generated by the thaj-~%i~~ion of data transfer on the Data Each timer in the MC6B40 has a corresponding write-only Control Register. Control Register #2 has a unique address space (R SO= 1, RS=O, RS2=O) and therefore may be written into at any time. The remaining Control Registers (#1 and #3) share the Address Register Select inputs. CR20 - The Space selected by a logic zero on all Bus. With the Pl~~$&lected, a low state on the PTM R/~ line enables the{~~t buffers and data is transferred from the MPU to the ~~~%nthe trailing edge of the E (Enable) clock. Alternat~~T ,J:&fider the same conditions) R/~= 1 and Enabl@~$~#!lows data in the PTM to be read by the MPU. >.:.+ *,,,.::>.i,,,.>.<,r .,, ~ !~%~LE (E CLOCK) - The E clock signal synchronizes da'~';ansfer between the MPU and the PTM. It also performs an equivalent synchronization function on the external clock, reset, and gate inputs of the PTM. least significant bit of Control Register #2 (CR20) is used as an additional addressing bit for Control Registers #1 and #3. Thus, with all Register selects and R/~ inputs at logic zero, Control Register #1 will be written into if CR20 is a logic one. Under the same conditions, Control Register #3 can also be written into after a RESET low condition has occurred, since all control register bits (except CR IO) are cleared. Therefore, one may write in the sequence CR3, CR2, CRI, INTERRUPT REQUEST (~Q) - The active low Interrupt Request signal is normallv tied directly (or through priority interrupt circuitry) to the ~ input of the MPU. This is an MOTOROLA 6 MC6840 DS9802R3 TABLE Register select Inputs RS2 0 RSI 0 RSO 0 CR20 CR20 =O =1 1 - REGISTER SELECTION Operations Rl~ Write =O Control Register #3 R/ti No Operation =1 Write Control Register #2 Register #1 Read Status Register Read Timer #l Counter Register .\, .,k.1+~,,,.., ~, , , ,:), "%? ~:: .*:,J! `~" :,: `I}*, \~,}> `$$.~.$, ,8, ~..~, ,*f~,! ,,, **} ~i, t$:,:+ `~,,>i!: .~~ .*:: .<&@ ,. ` \.* ,),$ ,,:$,,:$ ~:<,: ,.. ..... -',li+ %$' o o o 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 o 1 Write Control Write MSB Buffer Register Write Timer Write #1 Latches Register Read LSB Buffer Read Timer `*,\, MSB Buffer #2 Counter Register Write Timer #2 Latches Register Read LSB Buffer Read Timer Write MSB Buffer Write Timer #3 Counter Register #3 Latches Read LSB Buffer CR1O - The least significant bit of Control Register #1 is used as an Internal Reset bit. When this bit is a logic zero, all timers are allowed to operate in the modes prescribed by the remaining bits of the control registers. Writing a "one" into CRIO causes all counters to be preset with the contents of the corresponding counter latches, all counter clocks to be disabled, and the timer outputs and interrupt flags (Status Register) to be reset. Counter Latches and Control Registers are undisturbed by an Internal Reset and mav be written regardless of the state of CR IO. into the clock input circuitrv and the i@%'~:$p*@ounter #3. It can therefore be used with either the.int~,~clock (Enable) or an When initializing T~@3 consecutive E-cycles "%~:@~ with DMA), Control Register 3 must be initiali~~~~efore Timer Latch #3 to insure proper timer initiali~A%~,J `f"' .,<,:... s,::;:? $tito the divide-by-eight mode on The least significant bit of Control Register #3 is used as a selector for a -8 prescaler which is available with Timer #3 onlv. The prescaler, if selected, IS effectively placed TABLE between ~b!:% 2- CONTROL q#G~$?ER BITS rrupt Control !., (See Table 3) I Timer #X Counting TX configured TX configured Mode Control counting mode for normal (16-bit) for dual 8-bit counting mode CRX1 ~+:$ Timer #X Clock Source TX uses external clock source on ~ input TX uses Enable clock o 1 CR1O Internal O 1 Reset 8it to operate CR20 Control Register Address O 1 CR#3 mav be written CR#l mav be written x=2 Blt CR30 Timer #3 Clock Control O 1 T3 Clock is not prescaled T3 Clock is prescaled bv - B x=3 All ttmers allowed All timers held m preset state X=l MC6840 DS9802R3 MOTOROLA 7 Control Register Bits CR1O, CR20, and CR30 are unique in that each selects a different function. The remaining bits (1 through 7) of each Control Register select common functions, with a particular Control Register affecting only its corresponding timer. CRX1 - Bit 1 of Control Register #1 (CR11 ) selects whether an internal or external clock source is to be used with Timer #l. Similarly, CR21 selects the clock source for Timer #2, and CR31 performs this function for Timer #3. The function of each bit of Control Register "X" can therefore be defined as shown in the remaining section of Table 2. An interrupt flag is cleared by a Timer i.e., External RESET=O or Internal Reset will also be cleared by a Read Timer Counter vided that the Status Register has previously Reset con@tion, Bit (CR1O)= 1. It Command probeen read while - the interrupt flag was set. This condition on the Read Status Register-Read Timer Counter (R S-RT) sequence is designed to prevent missing interrupts which might occur after the status register is read, but prior to reading the Timer Counter. An Individual Interrupt Flag is also cleared by a Write Timer Latches (W) command or a Counter Initializqtf@ie (Cl) sequence, responding COUNTER provided that W or Cl affects to the individual Interrupt Flag, LATCH iNITIALl~TION Independent the,,,l~'~&~cor.~+ $! ~,~y$. ;% ,<.: y>.< *11: W,:+$ ,<+i.\.* , .. "".']:i ,,.+,..,. \ ~"t?<:?f{ ~,~ ,,~. ~ of a 16-bit CRX2 - Control Register Bit 2 selects whether the binary information contained in the Counter Latches (and subsequently loaded into the counter) is to be treated as a single 16-bit word or two 8-bit bytes. In the single 16-bit Counter Mode (CRX2= O) the counter will decrement to zero after N + 1 enabled [G= O) clock periods, where N is defined as the 16-bit number in the Counter Latches. With CRX2= 1, a similar Time Out will occur after (L+ I)*(M + 1) enabled clock periods, where L and M, respectively, refer to the LSB and MSB bytes in the Counter Latches. CRX3-CRX7 - Control Register 8its 3, 4, and 5 are explained in detail in the Timer Operating Mode section. Bit 6 is an interrupt mask bit which will be explained more fully in conjunction with the Status Register, and bit 7 is used to enable the corresponding Timer Output. A summary of the control register programming modes is shown in Table 3. Each of the three tim~$~~~~~sts addressable counter and a 16-bi$e~~~@sable latch. The counters are preset to the binary n~b~rs stored in the latches. Counter initialization res~+l~~kin Ne transfer of the latch contents to the counter. ~~}~Q@s in Table 4 regarding the binary number N, L, or$@~~*d into the Latches and their relationship to the ~,~~~,~,.waveforms and counter Time.,.~:2, >.b`.3* outs. :..~:..< ~.$,, ,,\\,,, Since the PT~,,da;~:$us is 8-bits wide and the counters are 16-bits wide, ~~~borary register (MSB Buffer Register) is provided. are iFmi$~~write of the the only" desired MSB register latch data. is for Three (as the Most- Signific(~tt.Q~]~ pr&~J~~~or addresses Buffer Register Ta&e 1), %ut they all lead to the same Buffer. Wy&$JBuffer will automatically be transferred indicated in Data from the into the Most- STATUS REGISTER/lNTERRUPT FLAGS Register four Qts f$?$niflcant Byte of Timer #X when a Write Timer #X Latches .$ `~$.,~$~kmand is performed. So it can be seen that the MC6840 f$~~~;has been designed to allow transfer of two bytes of data into >.!& "3 the counter latches provided first. The storage order must that the MS B is transferred be observed to ensure proper ,- The MC~ which contains has an internal Read-Only Status four Interrupt Flags, (The remaining of the register are not used, and defaults to zeros whe~~~; ing read.; Bits O, 1, and 2 are assigned to Timers 1, 20,3NQ @ respectively, as individual flag bits, while Bit 7 is a,<$o<~~~$~te Interrupt Flag. This flag bit will be asserted if{~~~$~'~<$~e individual flag bits is set while Bit 6 of the cor~~sw~$~$fig Control Register is at a logic one, The the composite Interrupt Flag bit can as: INT= where IIo CR16+ condil~~~;~~r asserting thwqfd~ be expressed .. ,Y, `!!?;?,.Jr, \,r ,,,. .x ),: 12. CR26&f~;$@% *jt latch oDeration. In many applications, the source of the data will be an M6800 Family MPU. It should be noted that the 16-bit store operations of the M68~ family microprocessors (STS and STX) transfer data in the order required by the PTM. A Store Index Register Instruction, for example, results in the MSB of the X register being transferred to the selected then the LSB of the X register being written into higher location. Thus, either the index register pointer may be transferred directly latch with a single instruction, A logic zero at the RESET input latches. In this case, all latches count of 65,53510. It is important into a selected address, the next or stack counter INT = Composl@~j~~$~&&pt Flag (Bit 7) 11= Timer #~Qln~~rrupt Flag (Bit O) 12= Tirq@,#2 `~kerrupt 13= ~~&~~2 Interrupt *), "v+y!~ , "* ` ,.:. ` ~l.l.,t(;f:j) ..:..l, Flag (Bit 1) Flag (Bit 2) also initializes the counter will assume a maximum to note that an Internal f:... hi:.,\,,..--\\ ... . ,.:) \:>I'~~\~.*.''.*. 1 ,!!s ...*., .... ,,, "i....~ "b !',..,?., . ,,,.. .L*.~..,, , o "!J::: -:..1 ~~ "'~$P;Rx4 ~cRp7 .:~,.>., \?y ,.t'..~,:,:t.t,.'~ o0 .:$ ! ~ ~Rx5 r 0 Continuous Frequency Continuous Pulse Width TABLE 3 - PTM OPERATING MODE SELECTION Operating Comparison Operating Mode: Mode: Mode: Gate 1 or Write Interrupt to Latches or Reset Causes Counter is< Counter Time Out Initialization 00 10 10 o01 101 o11 1 1 If Gate ~ Gate 1 or Reset Causes Counter Interrupt if Gate ~ If Gate ~ # Initialization Time Out Initialization T!me Out Comparison Mode: Is< Counter Is> Counter Single Shot Mode: Frequency Gate J or Write Mode: to Latches or Reset Causes Counter Comparison Interrupt Single Shot Mode: Gate I or Reset Causes Counter Mode: Interrupt If Gate $ Initialization ~ is> Counter Time Out 1 Pulse Width Comparison -- MOTOROLA 8 MC6840 DS9802R3 Reset ( Bit zero of Control the counter latches. COUNTER Y Counter INITIALIZATION Initialization Register 1 Set) has no effect on CLOCK clock Input programmed INPUT ~ C= ( + 8 PRESCALER a special -8 contains input its optional MODE) prescaler - External #3 is ripple do not clock represents to utilize input will prescaler setup case when Timer mode. (thd) The divide-by-8 as the transfer of data from counter; apply. ed, the (~) transition amount thus, counter an asynchronous is defined (tsu) and hold times pulse widths and process the latches to the counter with subsequent clearing of the individual Interrupt Flag associated with the counter. Counter Initialization always occurs when a reset condition (R ESET=O or CR1O= 1) is recognized. It can also occur - depending on Timer Mode - with a Write Timer Latches command or recognition of a negative transition of the Gate input. Counter recycling or re-initialization occurs when a negative counter transferred transition from of the clock an all-zero the Latches input state. is recognized In this case, after data the IS has reached As long as minimum transitions. However, are maintainall iriput that a clock a certain bef~en is recognize during in order to guarantee the current (tsYnc) time time is processed E cycle, is required of synchronization the ~3 transition possible following for the and the falling transition edge of Enable requirement ($$~~~&te 9). If the synchronization that the ~ E cycle. input -8 prescaler Characteristics, is n~t~~~it to the Counter. LINES the PTM has external output and ouputs clock are line. The inputs The maximum Operating clock in~uts will not be pro,Ge~~&&ntil the ~;t .\\"s: `~',:.e :, .<*,+?**. t ~~ frequency and +[~:~ak+~ duty cycles mode are :w~~@under the AC ASYNCHRONOUS and gate Inputs lNPUT/OUTPUT within as well as a counter Each of the three timers put is treated lnternall~$.th~ `-8 prescaler out..*.,\**, in the same manng$~s th~previouslv discussed are high-impedance, TTL-compatible lines capable of driving two standard TTL loads. CLOCK and ~will INPUTS accept ---- (Cl, C2, and~) asynchronous - Input ---- pins Cl, C2, level signals to accept asvnchronous~j~-~wrnpatlble or cl~~$lga%~~g functions signals which are used as triggers respectively, the to Timers 1, 2, and 3, TTL voltage decrement Timers 1, 2, and 3, respectively. The high and low levels of the external clocks must each be stable for at least one system clock period plus the sum of the setup and hold times for the clock inputs, The asynchronous clock rate can vary from dc to the limit Imposed by the Enable Clock Setup, and Hold times. The external clock inputs are clocked In by Enable pulses. Three -, Enable periods are used to synchronize and process the external clock. The fourth Enable pulse decrements the internal counter. This does not affect the input frequency,,,$f merely creates a delay between a clock input transitioK$&~~<, internal recognition of that transition by the PT1~~}@l~'& references to C inputs in this document relate t,~:lfi$$r~~l recognition of the input transition, Note that a Q~&$~fi~~~ or low level which does not meet setup and hol~i~,~~!~~cifications may require an additional Enable puls~:J,&~?~Wognltion. When observing recurring events, a lack{~~, ~~o~hronization will result in "jitter" being observed+:f~ Jh&Y'output of the PTM when using asynchronou:,,%/@$ and gate Input - ..**, signals. There are two types of ji~er.$ System jitter" is the result of the Input Enable, permitting signals be~&ti~*8i~ signal:$wlt~~ginal synchronization with setup and hold time the input between jitter, cycle, traninput if the and Th$~.$Y4mg inputs are clocked into the PTM bv `~~.'~ .~:t., E (enab~~''b~b% in the same manner as the previously That IS, a Gate transition Enable are met), of setup pulse is recognizsetup or low All (provided discusse,~~,~~~~ffiputs. anq:$~ld J,%: ,+~oc~ tlrne ed by,,th5~$~tTM on the fourth requirements plus the sum ~~.the Gate input period and the high and hold must be stable for at least one system times. in this document transition. directly affect the internal of ~ is therefore Independent relate to Internal $~~~~:~~?$rences to G transition **,. recognition The of the Gate -8 of the Input inputs of all timers selection, (01, 02, 03) 16-bit counter. The operation prescaler OUTPUTS TIMER duce - Timer for either waveform outputs 01, 02, or IS ac8-bit a and 03 are capable a defined Single-Shot complished operating square-wave duce a variable single-shot (CRX7) operating output write The sheet. other will is cleared, timer Timer modes. output duty of driving modes. The up to two TTL loads and proContinuous definition or Dual will output waveform Output either Single mode. bv selecting Single 16-bit 16-bit mode mode produce in the continuous and a single and pulse in the single-shot modes, The Dual 8-bit mode will prothe continuous Control output. regardless cycle Register If this bit of the a IS high the following cycle pulse in both the corresponding to be recognized by eith.~~~eblt time nearest sition or the subseque~~'%~~+dme. "Input signal first not jitter" ca~%$~ ,gw${ansitions great as the time negative One bit of each low (VOL) while enable Timer Timer at the is used to enable the output mode. will remain plus the svstem during one system If it is cleared Register. and the output transitiq~.go low during the first Single-Shot recogni$~d next cycle, or vice versa. See Figure 9. ~'~ ,k..i:~+ i:l?!:!?,,.+.s,::" J% ,i~$:.$ .,y)i~ ,i~,:i:> FIGURE 9 - INPUT JITTER .$,*,,, ~ *,!, .::, . ,:. .,~,.,".. \ .%) .,>?$,..t to the Control Continuous Modes are the and in (unless in typical onlv ones for which Applications modes. during CRX7=O) manual output response is defined of the output in this data signals Refer to the Programmable for a discussion appear and waveform Signals Fundamentals outputs Width Enable~ I"p"t Recog Input Either. Here ~ ~~ ~ Frequency Pulse comparison modes, + ~ System but the actual is not predictable applications. MC6840 DS9802R3 MOTOROLA 9 TIMER wide OPERATING variety MODES to operate effectively in a This is accomplished by using that wave the timer output is enabled OX, The type (CR X7= 1), either a square at via conof the - The MCWO has been designed of applications. or a variable Output, Register or internal duty Bit 2. cvcle waveform will be generated is selected Reset=O) transition the Timer Control dition of output three bits of each control register (CRX3, CRX4, and CRX5) to define different operating modes of the Timers. These modes are divided into modes, WAVE SYNTHESIS and WAVE MEASUREMENT and are outlined In Table 4. Either a Timer Reset (CR1O= recognition 1 or External of a negative Gate input results in Counter Initialization. A Write Timer latches command can be selected as a Counter Initialization signal bv clearing IS TABLE 4 - OPERATING Control Register CRX3 CRX4 CRX5 MODES Mode Svntheslzer Measurement CR X4. enabled by an absence of a TimeA~~eset The counter Timer Operating Con?lnuous Single-Shot o o 1 1 " ` 0 1 o 1 . " Frequency Comparison Pulse Width ComDarlson condition and a logic zero at the Gate Input. 1~,'%s''pk5-blt mode, tke counter WIII decrement on the flr~$'~~~~ cycle during or after the counter Initlallzatlon cvcl~~~~~%nues to decrement on each clock signal so long as.$~~~@alns low and no reset condition exists. A Counter Ti.@e,~&&~$the first clock after all counter bits = O) results in~~~x~~l~dlvldual Interrupt Flag being set and relnitlallzatlon.~~ f~''~ounter. In the Dual 8-bit mode (C RX2A= tk~~fer to the example n Figure 10 and Tables 5 and 6~$%~$.MSB decrements once for everv full countdown of t~$~~$~+ 1. When the LSB = O, the MSB is unchanged; on~~~n$$xt clock pulse the LSB IS reset . Defines Add!tlonal Timer Function SYNTHESIS is useful variable or SelectIon One cf the WAVE Operating Either generated Single-Shot operating programmable The WAVE cy Comparison tively. In addition ing control mode, symmetrical mode, mode, preset modes for cvclic dutycycle In use to IS the Continuous wave generation. can be the mode, waves the which in this mode. The other wave svnthesis is similar width. Continuous with a however, a single pulse is generated, modes include MEASUREMENT and Pulse Width the Frequenmodes which respec- Comparison are used to measure cyclic and singular modes pulse widths, to the four timer register in Table 4, the remaincounter initialization to the count in l~~k.~s~ Latches, and the MSB IS ` 3&$~~~3ing the normal 16-bit mode @.$<,. A special time-out condition exists for the dual 8-bit mode ,~~" and enabling or interrupt conditions, ,,,,:2 (CR X2= 1) if L=O. In this case, the counter WIII revert to a ,+*< mode similar to the single 16-bit mode, except Time Out oc.) \::* P WAVE SYNTHESIS MODES ,. ~ ~*\+ ~'~.,~ ,,> curs after M + 1` clock pulses. The output, if enabled, goes CONTINUOUS OPERATING MODE (TABLE 5k/f#$~\he low during the Counter Inltlallzatlon cycle and reverses state ,&'~:ye'~ith a continuous mode will synthesize a continuous at each Time Out. The counter remains cyclical (Is rebit is used to modify period timer proportional latches. to the preset number im~$~~t~dtticular initialized at each Time Out) and the Indlvldual Interrupt Flag Any of the timers in a continuous in the PTM ~$$&'"program`$, k. `?'s. mode ~~h~,~tr~ zeroes into co~~~o~k$$ster. Assuming is set when Time Out counters do not change, fi the clock frequency. occurs. If M = L=O, the Internal but the output toggles at a rate of - med to operate bits 3 and 5 of the corresponding MOTOROLA 10 MC6840 DS9802R3 ---- ---- TABLE Control Reg. Bit 5 8- FREQUENCY Counter Initiahzation COMPARISON MODE Counter Enable Flip-Flop Reset (CE) Interrupt Flag Mode Bit 3 Bit 4 Counter Enable Flip-Flop Set (CE) sat (1) al Et Before TO Before TO TO Before ~1 TO Before ~t Frequencv Comparison Pulse Width Comparison 1 1 1 1 0 0 1 1 0 1 0 1 ~ .j. ~+ TO)+ R ~1 .~+ R T+ RI q R c! .T+F ~ .~.~.r ---- --GI. W.R. I -------- GIW. R. I ---- ---- GI. W.R. I W+R+I W+R+I W+ R+I+G W+ R+I+G PIN ASSIGNMENT 02 rz a5 03 =7 RESET 3 4 26 25 24 6 23 22 8 21 20 19 -/ m9 RSO RS1 RS2 R/~ vc~ u 10 11 12 18 17 1 DO D1 D2 D3 D4 D5 D6 D7 E CS1 CTO MOTOROLA 13 ~ 13 16 14 15 MC6840 DS9802R3 The three differences between Timer Mode can be summarized Shot ed. 2. Counter 3. L= M =0 Aside WAVE TIME from Enable mode: is enabled 1, Output Single-Shot as attributes and Continous of the Single- generation until a new Counter Initialization cycle has been for only one pulse until it is reinitializIS independent disables of Gate or N =0 output. the two modes are identical, completed. When this internal bit is set, a negative transition of the Gate input starts a new Counter Initialization cvcle. ~TO is satisfied, since a T[me Out (The condition of ~1 q has occurred and no individual Interrupt has been generated. ) AnV of the timers within the PTM may be programmed to compare the period of a pulse (giving the frequencv after calculations) at the Gate input with the time period requested for Counter Time Out. A negative transition ~f the Gate Input enables the counter and starts a Coq{]J~$,J,n8Ed itlallzatlon cvcle -- provided that other condltlon~~+ a'9~m in Table 8, are satisfied. The counter decreme$~s~%veach clock signal recognized during or after Cou<~~##i\~~M'llzation until an Interrupt is generated, a Write Tj*"@~hes command is Issued, or a Timer Reset condl$j~'~o~;flrs. It can be seen from Table 8 that an inte(.[*@~<~@fidltion will be generated (f CRX5=0 and the pe~~d ,~f 'the pulse (single pulse or measured separately [d~etid-w' pulses) at the Gate input is less than the Count8{~~*,0ut period. If CR X5= 1, an interrupt is generated J&~$&~verse IS true. Assume now with Ct$,%$=~$ that a Counter Initialization has occurred and tha$i~~fl~~te input has returned low prior to Counter Time ,Q,ut.''Q~nce there is no Individual Interrupt Flag generated,,~~~]$$ ~,utomatlcally starts a new Counter initialization C@~~$$~e process will continue with frequencv comparis~o~$e~,~$ performed on each Gate input is determined cvcle until the mo~,~s changed, or a cvcle the ~~de~.mined limit. .4 :.\,.;*.,, h., ~,~.a to be above these differences, MEASUREMENT INTERVAL MODES - The Time Interval Modes are MODES the FrequencV (period) Measurement and Pulse Width Corrparison Modes, and are provided for those applications which require more flexibility of interrupt generation and Counter Initialization. Individual Interrupt Flags are set In these modes as a function of both Counter Time Out and transitions of the Gate Input. Counter fected bv Interrupt Flag status. A timer's output is normally ment mode, but it IS defined. Initialization IS also af- not used in a Wave MeasureIf the output is enabled, [t will operate as follows. During the period between relnitialization of the timer and the first Time Out, the output will be a logical zero. If the first Time Out is completed (regardless of Its method of generation), the output will go high. If further TO's occur, the output will change state at each completion of a Time-Out. The counter does operate in either Single 16-bit or Dual 8-bit modes as programmed bv CRX2. Other features of the Wave Measurement Modes are outlined Or Petiod in Table 7. Mode Frequency Comparison Measurement (CRX3= 1, CRX4=O) - The Frequency Comparison Mode with CR X5= 1 is straightforward. If Time Out occurs prior to the first negative transition of the Gate input after a Count@r Initialization cvcle, an Individual Interrupt Flag is set. *Q, counter IS disabled, and a Counter Initialization cvcle ~a~~o'~' `i?.$\\ @\,.,...?., begin u~il the interrupt flag is cleared and a nega$j$e~dn5~,2,,,,+,:,,... , `+!.\. tion on G is detected. ~$l~.y : ,,+: ~.'l, ..,<. ,, , If CR X5= O, as shown in Tables 7 and 8,,@~{~,;,W~upt IS generated if Gate input returns low prior tq$'$w''Out. Counter Time Out occurs first, the coukh~fi$ r~cvcled If a and &*'~ls#Width Comparison Mode (CRX3= 1, CRX4= 1) +&,~$~&~rnode is similar to the FrequencV Comparison Mode ex.t$:\\tfw>:: ~.(..,.~ept for a positive, rather than negative, transition of the "">? Gate input terminates the count. With CRX5= O, an lndivldf} `~ ual Interrupt Flag will be generated if the zero level pulse applied to the Gate input is less than the time period required for Counter Time Out, With CR X5= 1, the interrupt is generated when the reverse condition is true. As can be seen in Table 8, a positive transition of the Gate input disables the counter. With CR X5= O, it IS therefore possible to directlv obtain the width of anv pulse causing an interrupt. Similar data for other Time Interval Modes and conditions can be obtained, if two sections of the PTM are dedicated to the purpose. continues to decrement. A bit is set ~~ht$~~ti%e timer on the initial Time Out which precludes fw.tm~+$dividual interrupt *3),~.',,,: ` ::,, ,, ,., , ~,,/+.' +:::, <``. ?;/,, ,.:$, FIGURE 7 - OUTPUT DELAY cRX3 Application Frequency Comparison =1 Condition for Setting if Out !f Out if Out If Out Individual Gate (TO) Gate (TO) Gate (TO) Gate (TO) Input "Down Time" IS greater Input "Down Time" is less Input Period (1 /F) is greater Input Interrupt Period Flag (l/F) is less c q,%~,: : 5*X5 ; .J*, . ~ . s. `\y,.,,, .~l)+ ,,,.8' J" ",':*+ `\~.>;. ii .J:> !, `[:0 !: :k:\\ ;~j \3..x/ ~ ~ s~ij,.\$ ....,, ,,.s%}::,:,? .s. .'. .,>,,, \ t qj>~,, ; i~, <,:.-.,,. ~:<$.,F >,,>,, `t.., 1 o 1 Interrupt than Generated Time Counter Frequency Comparison Interrupt than Generated Time Counter o 1 Pulse Width Comparison Interrupt than Generated Time Counter Pulse Width Comparison Interrupt than Generated Time Counter MOTOROLA 12 ------- --- .-- MC6840 DS9802R3 .. . .. . . FIGURE 10 - (Continuous TIMER OUTPUT WAVEFORM Dual 8-Bit Mode Using Internal EXAMPLE Enable) "Time Example: Contents Contens of of MSB LSB = 03 = M = 04 = L out I ~M(L+l)+l~L4 ---- ~ I I Algebraic 03(04+ 16 Enables Expression 1)+ 1 = II 2.4 0.4 V Counter Output 1: l\ II ~ 1A ~m `L II 1 Enable (System 02) II _l+L~,+L~l 5 Enable Pu Ises I I Ii I I * I I I I T. (M M(L + 1)(L+ 1) = Period LOW portion of period ,+, MSB to Respective Latches and Latches on the negattve MSB bv one .$.*\$k trans[f~o~!of +$&ternal the Enable transition Clock 1[ II II II ~ 1, (M+l)(L+l) id: ~ 5 Enable Pulses +L~ 5 Enable Pulses , ~L I \\ ,,,>:! $ >$',i ,<~~t ~ ,, J ,:. ?.,.* `$ ,,,,:.. ,5, ,,,L,X ,.i: `.''*:..{:, ,,s~?p%k *$ & .,:-" ,,,,, iv ` *'.$&*J , !,:. 4 Enable ..$,\\.* . ..!:, .: Pu Ises $~,k .::>.,,+ 1 + LV,*J:,,::'"" i. 5 E q,~j: ~k$! p u+!?~~ ,*S +$? . .,,,f,? ~ , . "*Q. @kr.\:27,, .b,;:t. .:6 ~ ,~+s~'. ?*, ~;, <~:;*:> ~(~ ~ ` ~$~~$ $~':~.. v II II Il., , [ \ ki\\ ,k..,&'"" ~.~:: .?$>. ,. :'?$}> ; A l& br$l&" E xpression ..$j~9f$?y\(03 + 1) = 20 Pulses Enable or + 1) + 1 = width and L = Pulse *Preset * *Preset LSB LSB to LSB Decrement on th~~;~~,ti;$ .. k ~~"h , ,$y `:$s~$ ,*,, .,\.,.., , .t,te t$~,)?it $,<;,} of the Enable Y The tilscussion of the Continuous Mode has assumed that the application requires an output signal. It should be noted. * ,+.: .{..' that the Timer operates in the same manner with the out~ti%$,, disabled (C RX7=O). A Read Timer Counter comman&~s `*: ~?$: J?.S:J:>. valid regardless of the state of CR X7. ` .,,`k'." `"'" ,$.:J'? !,$. ,.. ,., \i.+::i~\*\$:).\, SINGLE-SHOT TIMER MODE - This mode~st~%'~%$'al to the Continuous Mode with three exceptioq~'$~$$ first of these is obvious from the name - the o~~pu~it~turns to a low level after the initial Time Out a~~:r~w~ns low until another Counter Initialization cyclec,$$~~s,$ As indicated in Table 6, the inte$~a~~ountlng mechanism remains cvclical in the Single-$@@~;~@de. Each Time Out of .:..$.., `,* ., ":':::.:.,:,, ~ >J:,i. ,,,. TABLE 6- SINGLE-SHOT $1': ~' ,*) :,+ ., \ "des syb$h~;s'm `Q~,\ ~$>;,<> ..,, . $\ ~ I SINGLE-SHOT (CRX3 `0, CR X7= +U *the counter results in the setting of an Individual Flag and re-initialization of the counter. The second Continuous major difference modes between is that the internal counter Interrupt and is not the Single-Shot enable dependent on the Gate input level remaining In the low state for the Single-Shot mode. Another special condition is Introduced in the Single-Shot mode. If L= M=O (Dual 8-bit) or N=O (Single 16-bit), the output goes low on the first clock received during or after Counter Initialization. The output remains low until the Operating Mode is changed or nonzero data IS written Into the Counter of each clock OPERATING MODE I, CRX5= 1) Waveforms Timer Output (OX) Latches. period. Time Outs continue to occur at the end MODES <$~$~~~1 Register ..@ r ;?*X2 CRX4 $, , `i<* Yi* !.l:., * .J:$~ >' ~}.: $<,* ,. `< tfr:$ 0 0 :..i$>% kw+~s, ~t,-:. ,%. `.. .,:,.-:. ~>::, ,,\\\: ~% .,. 0 1 Initialization/Output Counter Initialization ~L+W+R ~F_y'N+l'T'lo ~$+R 1 0 6J +W+R ~(L+''(q::~'L')(M+''(T)~ 1 1 5$+R lo TO TO Symbols are as defined in Table 5. MC6840 DS9802R3 MOTOROLA 11 PACWGE DIMENSIONS -- NOTES: 1. POSITIONAL TOLERANCE OF LEAOS (01, SHALL BE WITHIN 0.25rnrn(0.OID) AT MAXIMUM MATERIAL CONOITION, IN RELATION TO SEATING PLANE ANO EACH OTHER. OIMENSION L TO CENTER WHEN FORMEO PARALLEL. OIMENSION B DOES NOT MOLO FLASH. OF LEAOS IN CLUOE ,8 h nfitinfinfifi h fin AA ,,, , 2, 3. P SUFFIX PLASTIC CASE PACKAGE 71002 L: --H- -G- A Ni , 4 , Lc- \ F - - --- K D SF*T,,Z ?,l,,[ --~ ~ --- NOTES 1. OIM ~ 2. POSITIONAL IS OAT,&~ T~j~~O+&&,AOS: S SUFFIX CERDIP CASE PACKAGE 7S01 4 5 DIM A&#Q$>J,N5~UOES OIM ~k::YY&*ENTER MENISCUS. OF LEA05 r: 6. OIM~&lONING AN OTOLERANCING ,,~~ PER ~NSl Y14.5, 1973. ,3;:E:;"' rA -)~jjF L `1 -+y[f~k ~G~ ~ F +:\ i, ,, ..! ."$v$>>t.$?:' ~y"'" -.:::: ,)$ ~,:: . .,*`.,'!!.,.~. . .,,.,, ~.:..~<. ,.,, ::wD*t,>+ ..,.> ~M I ,>, .+ ?:i:, `~,,:t ,$$. , .*:,* , ,i$: ,ij"~ " %;;* "i,<,!l ~::~,, \*t: ,!t, .<%:,i,,$ ,,.i,. .",?:* J'$! .. ~.,, ~~',> .. `$:s:,:, ,,$$ .1:$.. `\ .:;$. .{J:+ ,:.,:$ ~.{?::\\, :,, .~> `~ ~>$t. .,, ,,\i.$,$$< \.**...F?' ~,$ii, .,ii:~:!:it :<-,:,, kb, "*{*, t ..} `\\ k*i:.. , :,$,,;; ,:..!', hotorola does under not its reserves assume patent the any rights right Iiabilitv to make arising changes out without further notice or use to any products herein to improve reliability, herein; neither function does or design. it convev Motorola any license of the application of anv product or circuit described nor the rights of others. Motorola products are not authorized for use as components in life suppofl devices or systems intended for surgical implant into the body or intended to support or sustain life. Buver agrees to notify Motorola of anv such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended. Motorola and @ are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity/Affirmative Action EmploVer. Literature Distribution Centers: -. -o MMOrOROLA .-,,,,5., ,.,.,,, 1,",. 7-88 USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Center; 88 Tanners Drive, Blakelands Milton KeVnes, MK145BP, England. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; PO. Box 80300; Cheung Sha Wan Post Office; Kowloon Hong Kong. MC6840 .=0 C578Z4 5.WO YCACM IWERW DS9802R3 |
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